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  rev.06(aug.18.2010) 1 FM25Q16 FM25Q16 16mbit serialflashmemorywith4kbsectors,dualandquadi /ospi
rev.06(aug.18.2010) 2 FM25Q16 documentstitle 16mbitserialflashmemorywith4kbsectors,dualand quadi/ospi revisionhistory revision no. history draftdate remark 0.0 initialdraft jul.03,2009 preliminary 0.1 correcttypo. aug.07.2009 preliminary 0.2 memorystatusregistermemoryprotection features jun.18.2010 final 0.3 dcelectricalcharacteristics inputlowvoltages(vccx0.2) inputhighvoltages(vccx0.8) jun.29.2010 final 0.4 instructionsettable1 operatingranges csactivesetuptime csactiveholdtime jul.22.2010 final 0.5 revisionnochange revisionhistorychange correcttypo. jul.30.2010 final 0.6 writestatusregister(01h) previousbits=>clearedto0change readinstructionstshsl20ns=>10nschange aug.18.2010 final
rev.06(aug.18.2010) 3 FM25Q16 tableofcontents 1. general description............................. ................................................... ................................5 2. features........................................ ................................................... .............................................5 3. pin configuration 8pin soic 150mil/208mil.... ................................................... ...............6 4. pad configuration 8contact wson 6x5mm......... ................................................... .............6 5. pin configuration pdip 300mil . ...........................6 6. pindescriptionsoic208mil,pdip300miland wson6x5mm ......................7 7. pin configuration 8pin soic 300mil............ ................................................... .....................7 8. pin description soic 300mil................... ................................................... ..........................8 8.1 package type................................. ................................................... .............................9 8.2 chip select (/cs)........................ ................................................... .................................9 8.3 serial data input / output .............................9 8.4 write protect (/wp)............................ ................................................... ..........................9 8.5 hold (/hold)................................... ................................................... ........................ 9 8.6 serial clock (clk)............................ ................................................... ...........................9 9. block diagram................................... ................................................... .....................................10 10. function description........................... ................................................... ...............................11 10.1 spi opertations.............................. ................................................... ......................11 10.1.1 standard spi instructions............... ................................................... .............11 10.1.2 dual spi instructions................... ................................................... ................11 10.1.3 quad spi instructions..................... ................................................... .............11 10.1.4 hold function........................... ................................................... ...................11 10.2 w rite protection......... ..................... ........................................12 10.2.1 write protect features................... ................................................... ..........12 11. control and status registers ................................................... ........................13 11.1 status register.............................. ................................................... ....................13 11.1.1 busy.................................... ................................................... .......................13 11.1.2 write enable latch (wel)................ ................................................... ...........13 11.1.3 blockprotect bits (bp2, bp1, bp0)...... ................................................... .......13 11.1.4 top/bottom block protect (tb)........... ................................................... .........13 11.1.5 sector/block protect (sec).............. ................................................... ...........13 11.1.6 status register protect (srp1, srp0).... ................................................... ...14 11.1.7 erasesuspendstatus(sus) .. .. 14 11.1.8 quad enable (qe) ................................................... .......14 11.1.9 status register memory protection......... ................................................... ..16 11.2 instructions.................................. ................................................... ...................... 17 11.2.1 manufacturer and device identification.. ................................................... .... 17 11.2.2 instruction set table1.................. ................................................... .............. 18 11.2.3 instruction set table2.................... ................................................... ............ 19 11.2.4 write enable (06h) . . .. . 20 11.2.5 write disable (04h) ................... 20 11.2.6 readstatusregister1(05h)andreadsta tusregister2(35h)... ........21 11.2.7 write status register (01h) ..................... 22 11.2.8 read data (03h) .....................23
rev.06(aug.18.2010) 4 FM25Q16 11.2.9 fast read (0bh) . ........................................24 11.2.10 fast read duali/o (bbh). .. .. . ............... .25 11.2.11 fast read quad i/o (ebh) .. .. . ............... 27 11.2.12 page program (02h). .. ....................... 29 11.2.13 quaddatainputpageprogram(32h). .. .........................30 11.2.14 quad data page program (38h). .... ......................... 31 11.2.15 sector erase (20h). ............................ 32 11.2.16 32kb block erase (52h). ........................... 33 11.2.17 64kb block erase (d8h). .. ............................ 34 11.2.18 chip erase (c7 / 60h). ........................35 1 1 . 2 . 1 9 e ras e s u s p e n d (7 5 h ) . . . .. . .. .. .. .. . .. .. .. .. . 36 11.2.20 erase resume (7ah) . ....................... 36 11.2.21 powerdown (b9h). ............................ 37 11.2.22 release powerdown / deviceid (abh)..... ..................................................3 8 11.2.23 read manufacturer / device id (90h,efh,df h). . .... 40 11.2.24 jedec id (9fh). ................................................... .................... 43 11.2.25 mode bit reset (ffh). ................................................... ........ 44 11.2.26 enter secured otp (b1h). ................................................... ........ 45 11.2.27 exit secured otp (c1h). ................................................... .......... 45 11.2.28 read security register (2bh).. ................................................... ........ 46 11.2.29 write security register (2fh). ................................................... .. 47 11.2.30 4kbit secured otp....................... ................................................... ......... 48 12. electrical characteristics ................................................... .................49 12.1 absolute maximum ratings.................... ................................................... ...................49 12.2 operating ranges.............................. ................................................... ....................... 49 12.3 endurance and data retention ................................................... ........... 50 12.4 powerup timing and write inhibit threshold... ................................................... .........50 12.5 dc electrical characteristics................. ................................................... .....................51 12.6 ac measurement conditions.................... ................................................... ................. 52 12.7 ac electrical characteristics................. ................................................... ..................... 53 12.8 ac electrical characteristics (contd) ................................................... ...54 12.9 serial output timing.......................... ................................................... ........................55 12.10 input timing................................. ................................................... ............................ 55 12.11 hold timing................................. ................................................... ............................. 55 13. package specification.......................... ................................................... ........................... 56 13.1 8pin soic 150mil ................................................... ......................56 13.2 8pin soic 208mil ................................................... ......................57 13.3 8pin pdip 300mil .......................... ................................................... ........................ 58 13.4 8contact 6x5 wson........................... ................................................... ..................... 59 13.5 8contact 6x5 wson contd.................... ................................................... ................. 60 13.6 16pin soic 300mil................. ................................................... ................................ 61 14. ordering information........................... ................................................... ............................62
rev.06(aug.18.2010) 5 FM25Q16 1.generaldescription the FM25Q16 serial flash memory provides a storage solution for systems with limited space, pins and power. the 25q series offers flexibility a nd performance well beyond ordinary serial flashdevices.theyareidealforcodeshadowingto ram,executingcodedirectlyfromdual/quad spi (xip) and storing voice, text and data. the dev ices operate on a single 2.7v to 3.6v power supply with current consumption as low as 5ma activ e and 1a for powerdown. all devices offeredinspacesavingpackages. the FM25Q16 array is organized into 8,192 programma ble pages of 256bytes each. up to 256 bytescanbeprogrammedatatimeusingthepagepr ograminstructions.pagescanbeerasedin groupsof16(sectorerase)groupsof128(32kbblo ckerase),groupsof256(64kbblockerase) ortheentirechip(chiperase).theFM25Q16has1, 024erasablesectorsand64erasableblocks respectively.thesmall4kbsectorsallowforgreat erflexibilityinapplicationsthatrequiredataan d parameterstorage. the FM25Q16 supports the standard serial peripheral interface (spi), and a high performance dual output as well as dual i/o spi using pins: ser ial clock, chip select, serial data i/o0(di), serial data i/o1(do). spi clock frequencies of up t o 104mhz are supported allowing equivalent clock rates of208mhz for dual output and 416mhz fo r quad output when using thefast read dual/quad output instructions. these transfer rates are comparable to those of 8 and 16bit parallelflashmemories. aholdpin,writeprotectpinandprogrammablewrit eprotection,withtoporbottomarraycontrol, providefurthercontrolflexibility.additionally, thedevicesupportsjedecstandard manufacturer anddeviceidentificationwitha4kbitsecuredotp . 2.features spiflashmemory FM25Q16:16mbit/2mCbyte 256bytesperprogrammablepage 4kbitsecuredotp standard,dualorquadspi standardspi:clk,/cs,di,do,/wp,/hold dualspi:clk,/cs,io 0 ,io 1 ,/wp,/hold quadspi:clk,/cs,io 0 ,io 1 ,io 2 ,io 3 highestperformanceserialflash upto7xthatofordinaryserialflash 104mhzclockoperation 208mhzequivalentdualspi 416mhzequivalentquadspi 50mb/scontinuousdatatransferrate 31mb/srandomaccess(32bytefetch) comparabletox16parallelflash packagematerial fidelixallproductgreenpackage leadfree rohscompliant halogenfree flexiblearchitecturewith4kbsectors uniformsectorerase(4kbyte) blockerase(32kand64kbytes) programoneto256bytes upto100,000erase/writecycles 20yearsdataretention erasesuspend&resume lowpower,widetemperaturerange single2.7to3.6vsupply 5maactivecurrent,<1apowerdown(typ.) 40 to+85 operatingrange advancedsecurityfeatures softwareandhardwarewriteprotect toporbottom,sectororblockselection lockdownandotpprotection spaceefficientpackaging 8pinsoic150mil 8pinsoic208mil 8padwson6x5mm 16pinsoic300mil 8pindip300mil
rev.06(aug.18.2010) 6 FM25Q16 3.pinconfigurationsoic150mil/208mil vcc di(io 0 ) clk /hold(io 3 ) / cs gnd / wp(io 2 ) do(io 1 ) 1 8 7 65 4 3 2 vcc di(io 0 ) clk /hold(io 3 ) / cs gnd / wp(io 2 ) do(io 1 ) 1 8 7 65 4 3 2 figure1a.FM25Q16pinassignments,8pinsoic208 mil 4.padconfigurationwson6x5mm vcc di(io 0 ) clk /hold(io 3 ) /cs gnd /wp(io 2 ) do(io 1 ) 1 87 6 5 4 3 2 vcc di(io 0 ) clk /hold(io 3 ) /cs gnd /wp(io 2 ) do(io 1 ) 1 87 6 5 4 3 2 figure1b.FM25Q16padassignments,8padwson 5.pinconfiguration8pinpdip300mil /cs do(io1) /wp(io2) gnd vcc /hold(io3) clk di(io0) figure1c.FM25Q16pinassignments,8pinpdip300 mil
rev.06(aug.18.2010) 7 FM25Q16 6.pindescriptionsoic208mil,pdip300milwson 6x5mm pinno. pinname i/o fuction 1 /cs i chipselectinput 2 do(io1) i/o dataoutput(datainputoutput1)*1 3 /wp(io2) i/o writeprotectinput(datainputoutp ut)*2 4 gnd ground 5 di(io0) i/o datainput(datainputoutput0)*1 6 clk i serialclockinput 7 /hold(io3) i/o holdinput(datainputoutput3)* 2 8 vcc powersupply *1io0andio1areusedfordualandquadinstructi ons *2io0 io3areusedforquadinstructions 7.pinconfigurationsoic300mil /hold(io 3 ) vcc n/c n/c n/c n/c /cs do(io 1 ) clk n/c n/c n/c n/c gnd /wp(io 2 ) di(io 0 ) 1 4 3 25 7 68 16 13 14 15 12 10 11 9 /hold(io 3 ) vcc n/c n/c n/c n/c /cs do(io 1 ) clk n/c n/c n/c n/c gnd /wp(io 2 ) di(io 0 ) 1 4 3 25 7 68 16 13 14 15 12 10 11 9 figure1d.FM25Q16pinassignments,16pinsoic300 mil
rev.06(aug.18.2010) 8 FM25Q16 8.pindescriptionsoic300mil padno. padname i/o fuction 1 /hold(io3) i/o holdinput(datainputoutput3)*2 2 vcc powersupply 3 n/c noconnect 4 n/c noconnect 5 n/c noconnect 6 n/c noconnect 7 /cs i chipselectinput 8 do(io1) i/o dataoutput(datainputoutput1)*1 9 /wp(io2) i/o writeprotectioninput(datainputo utput2)*2 10 gnd ground 11 n/c noconnect 12 n/c noconnect 13 n/c noconnect 14 n/c noconnect 15 di(io0) i/o datainput(datainputoutput0)*1 16 clk i serialclockinput *1io0andio1areusedfordualandquadinstructi ons *2io0_io3areusedforquadinstructions
rev.06(aug.18.2010) 9 FM25Q16 8.1packagetypes FM25Q16isofferedinan8pinplastic150milwidt hsoic,8pinplastic208milwidthsoic,6x5 mmwson,8pinpdipand16pinplastic300milwidt hsoicasshowninfigure1a,1b,1cand1d respectively.packagediagramsanddimensionsarei llustratedattheendofthisdatasheet. 8.2chipselect(/cs) thespichipselect(/cs)pinenablesanddisables deviceoperation.when/csishighthedevice isdeselectedandtheserialdataoutput(do,orio 0,io1,io2,io3)pinsareathighimpedance. whendeselected,thedevicepowerconsumptionwill beatstandbylevelsunlessaninternalerase, programor writestatus register cycle is in progre ss.when /cs is brought low the device willbe selected,power consumptionwill increasetoactive levels and instructionscan be written to and read data from the device. after powerup, /cs must transition from high to low before a new instructionwillbeaccepted.the/csinputmusttr ackthevccsupplylevelatpowerup(seewrite protectionandfigure30).ifneededapullupres isteron/cscanbeusedtoaccomplishthis. 8.3serialdatainput,outputandios(di,doandi o0,io1,io2,io3) the FM25Q16 supports standard spi, dual spi and qua d spi operation. standard spi instructionsusetheunidirectionaldi(input)pin toseriallywriteinstructions,addressesordatat o the device on the rising edge of the serial clock ( clk) input pin. standard spi also uses the unidirectionaldo(output)toreaddataorstatusf romthedeviceonthefallingedgeofclk. dual and quad spi instructions use the bidirectiona l io pins to serially write instructions, addressesordatatothedeviceontherisingedge ofclkandreaddataorstatusfromthedevice onthefallingedgeofclk.quadspiinstructionsr equirethenonvolatilequadenablebit(qe)in statusregister2tobeset.whenqe=1the/wppin becomesio2and/holdpinbecomesio3. 8.4writeprotect(/wp) thewriteprotect(/wp)pincanbeusedtoprevent thestatusregisterfrombeingwritten.usedin conjunctionwiththestatusregistersblockprotec t(sec.tb.bp2,bp1andbp0)bitsandstatus registerprotect(srp)bits,aportionortheentir ememoryarraycanbehardwareprotected.the /wp pin is active low. when the qe bit of status re gister2 is set for quad i/o, the /wp pin (hardwarewriteprotect)functionisnotavailable sincethispinisusedforio2.seefigure1a,1b, 1cand1dforthepinconfigurationofquadi/oope ration. 8.5hold(/hold) the/holdpinallowsthedevicetobepausedwhile itisactivelyselected.when/holdisbrought low,while/csislow,thedopinwillbeathighi mpedanceandsignalsonthediandclkpinswill beignored(dontcare).when/holdisbroughthigh ,deviceoperationcanresume. the/hold functioncanbeusefulwhenmultipledevicesaresh aringthesamespisignals.the/holdpinis active low.when the qe bit of status register2 is set quad i/o, the /hold pin function is not availablesincethispinusedforio3.seefigure1 a,1b,1cand1dforthepinconfigurationofquad i/ooperation. 8.6serialclock(clk) the spi serial clock input (clk) pin provides the t iming for serial input and output operations. (seespioperations)
rev.06(aug.18.2010) 10 FM25Q16 9.blockdiagram xxff 00h xxf 000h xxffffh xxf 0ffh sector 15 (4kb) xxef 00h xxe 000 h xxefffh xxe 0ffh sector 14 (4kb) xxdf 00h xxd 000 h xxdfffh xxd 0ffh sector 13 (4kb) xx2f00h xx 2000 h xxffffh xxf 0ffh sector 2(4kb) xx1f00h xx 1000 h xx1fffh xx10ffh sector 1(4kb) xx0f00h xx 0000 h xx0fffh xx00ffh sector 0(4kb) write control logic status register spi commandand controllogic highvoltage generators pageaddress latch /counter byteaddress latch /counter columndecode and 256 bytepagebuffer write protect logic and row decode blocksegmentation /wp (io 2 ) /hold (io 3 ) clk cs di(io 0 ) do (io 1 ) data 1fff 00h 1ff000 h 1fffffh 1ff0ffh block 31 (64kb ) 10ff00h 100000 h 10ffffh 1000 ffh block 16 (64 kb) 0fff 00h 0f0000 h 0fffffh 0f00ffh block 15(64kb ) 08ff00h 080000 h 08ffffh 0800 ffh block 8(64 kb) 07ff00h 070000 h 07ffffh 0700 ffh block 7(64 kb) 00ff00h 000000 h 00ffffh 0000 ffh block 0* (64 kb) beginning pageaddress ending page address FM25Q16 xxff 00h xxf 000h xxffffh xxf 0ffh sector 15 (4kb) xxef 00h xxe 000 h xxefffh xxe 0ffh sector 14 (4kb) xxdf 00h xxd 000 h xxdfffh xxd 0ffh sector 13 (4kb) xx2f00h xx 2000 h xxffffh xxf 0ffh sector 2(4kb) xx1f00h xx 1000 h xx1fffh xx10ffh sector 1(4kb) xx0f00h xx 0000 h xx0fffh xx00ffh sector 0(4kb) write control logic status register spi commandand controllogic highvoltage generators pageaddress latch /counter byteaddress latch /counter columndecode and 256 bytepagebuffer write protect logic and row decode blocksegmentation xxff 00h xxf 000h xxffffh xxf 0ffh sector 15 (4kb) xxef 00h xxe 000 h xxefffh xxe 0ffh sector 14 (4kb) xxdf 00h xxd 000 h xxdfffh xxd 0ffh sector 13 (4kb) xx2f00h xx 2000 h xxffffh xxf 0ffh sector 2(4kb) xx1f00h xx 1000 h xx1fffh xx10ffh sector 1(4kb) xx0f00h xx 0000 h xx0fffh xx00ffh sector 0(4kb) write control logic status register spi commandand controllogic highvoltage generators pageaddress latch /counter byteaddress latch /counter columndecode and 256 bytepagebuffer write protect logic and row decode blocksegmentation /wp (io 2 ) /hold (io 3 ) clk cs di(io 0 ) do (io 1 ) data 1fff 00h 1ff000 h 1fffffh 1ff0ffh block 31 (64kb ) 10ff00h 100000 h 10ffffh 1000 ffh block 16 (64 kb) 0fff 00h /wp (io 2 ) /hold (io 3 ) clk cs di(io 0 ) do (io 1 ) data 1fff 00h 1ff000 h 1fffffh 1ff0ffh block 31 (64kb ) 10ff00h 100000 h 10ffffh 1000 ffh block 16 (64 kb) 0fff 00h 0f0000 h 0fffffh 0f00ffh block 15(64kb ) 08ff00h 080000 h 08ffffh 0800 ffh block 8(64 kb) 07ff00h 070000 h 07ffffh 0700 ffh block 7(64 kb) 00ff00h 000000 h 00ffffh 0000 ffh block 0* (64 kb) 0f0000 h 0fffffh 0f00ffh block 15(64kb ) 08ff00h 080000 h 08ffffh 0800 ffh block 8(64 kb) 07ff00h 070000 h 07ffffh 0700 ffh block 7(64 kb) 00ff00h 000000 h 00ffffh 0000 ffh block 0* (64 kb) beginning pageaddress ending page address FM25Q16
rev.06(aug.18.2010) 11 FM25Q16 10. functionaldescription 10.1spioperations 10.1.1standardspiinstructions theFM25Q16isaccessedthroughanspicompatibleb usconsistingoffoursignals:serialclock (clk). chip select (/cs), serial data input (di) an d serial data output (do). standard spi instructionsusethediinputpintoseriallywrite instructions,addressesordatatothedeviceont he risingedgeofclk.thedooutputpinisusedtore addataorstatusfromthedeviceonthefalling edgeofclk. spi bus operation modes 0 (0, 0) and 3 (1, 1) are s upported. the primary difference between mode0andmode3concernsthenormalstateofthe clksignalwhenthespibusmasterisin standby and data is not being transferred to the se rial flash. for mode 0 the clk signal is normallylowonthefallingandrisingedgesof/cs .formode3theclksignalisnormallyhighon thefallingandrisingedgesof/cs. 10.1.2dualspiinstructions the FM25Q16 supports dual spi operation when using the fast read dual i/o (bb hex) instruction.thisinstructionallowsdatatobetra nsferredtoorfromthedeviceatthreetofourthe rateordinaryserialflashdevices.thedualreadi nstructionisidealforquicklydownloadingcode toramuponpowerup(codeshadowing)orforexecut ingnonspeedcriticalcodedirectlyfromthe spibus(xip).whenusingdualspiinstructionsthe dianddopinsbecomebidirectionali/0pins; io0andio1. 10.1.3quadspiinstructions theFM25Q16supportsquadspioperationwhenusing thefastreadquadi/o(ebhex).this instructionallowsdatatobetransferredtoorfro mthedevicesixtoseventimestherateofordinar y serial flash. the quad read instruction offers a si gnificant improvement in continuous and randomaccesstransferratesallowingfastcodesha dowingtoramorexecutiondirectlyfromthe spibus(xip).whenusingquadspiinstructionthe dianddopinsbecomebidirectionalio0and io1,andthe/wpand/holdpinsbecomeio2andio3 respectively.quadspiinstructionsrequire thenonvolatilequadenablebit(qe)instatusreg ister2tobeset. 10.1.4holdfunction the/holdpinisusedtopauseaserialsequenceof thespiflashmemorywithoutresettingthe clockingsequence.toactivatethe/holdmode,the /csmustbeinactivelowstate.the/hold modebeginswhentheclkinactivelowstatecoinci deswiththefallingedgeofthe/holdsignal. theholdmodeendswhenthe/holdsignalsrisinge dgecoincideswiththeclkinactivelow state. ifthefallingedgeofthe/holdsignaldoesnotco incidewiththeclkinactivelowstate,thenthe deviceentersholdmodewhentheclkreachesthene xtactivelowstate.similarly,iftherising edgeofthe/holdsignaldoesnotcoincidewiththe clkinactivelowstate,thenthedeviceexits inholdmodewhentheclkreachesthenextactivel owstate.seefigure.2forholdcondition waveform. if/csisdrivenactivehighduringaholdconditio n,itresetstheinternallogicofthedevice.as long as /hold signal is low, the memory remains in the hold condition. to resume communicationwiththedevice,/holdmustbedriven activehigh,and/csmustbedrivenactive low.see12.11forholdtiming.
rev.06(aug.18.2010) 12 FM25Q16 figure2.holdconditionwaveform 10.2writeprotection applications that use nonvolatile memory must take consideration the possibility of noise and otheradversesystemconditionsthatmaycompromise dataintegrity.toaddressthisconcernthe FM25Q16providesseveralmeanstoprotectdatafrom inadvertentwrites. 10.2.1writeprotectfeatures  deviceresetswhenvccisbelowthreshold  timedelaywritedisableafterpowerup  writeenable/disableinstructionsandautomaticwr itedisableafterprogramanderase  softwareandhardware(/wppin)writeprotectionu singstatusregister  writeprotectionusingpowerdowninstruction  lockdownwriteprotectionuntilnextpowerup  onetimeprogram(otp)writeprotection upon powerupat power down the FM25Q16 will mainta ina reset condition while vcc is below thethresholdvalueofvwi,(seepoweruptimingan dvoltagelevelsandfigure30).whilereset, all operations are disabled and no instruction is r ecognized. during powerup and after the vcc voltageexceedsvwi,instructionsrelatedwithall programanderasearefurtherdisabledforatime delay of tpuw. this includes the write enable, page program, sector erase, block erase, chip erase,writesecurityregisterandthewritestatus registerinstructions.notethatthechipselect pin(/cs)musttrackthevccsupplylevelatpower upuntilthevccminlevelandtvsltimedelay isreached.ifneededapullupresisteron/cscan beusedtoaccomplishthis. after powerup the device is automatically placed i n a writedisabled state with status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program,sectorerasechiperaseorwritestatusre gisterandtheninstructionswillbeaccepted. after completing a program, erase or write instruct ion the write enable (wel) is automatically clearedtowritedisabledstateof0. software controlled write protection is facilitated using the write status register instruction and settingthe status register protect (srp) and block protect (sec, tb, bp2, bp1, and bp0) bits. thesesettingallowaportionorallthememoryto beconfiguredasreadonly.usedinconjunction withthewriteprotect(/wp)pin,changestothest atusregistercanbeenabledordisabledunder hardware control. see status register for further i nformation. additionally, the powerdown instructionoffersanextralevelofwriteprotecti onasallinstructionsareignoredexceptforrelea se powerdowninstruction.
rev.06(aug.18.2010) 13 FM25Q16 11.controlandstatusregister thereadstatusregisterinstructioncanbeusedto providestatusontheavailabilityoftheflash memoryarray,ifthedeviceiswriteenabledordis abled,thestateofwriteprotectionandthequad spi setting. the write status register instruction can be used to configure the devices write protection features and quad spi setting.write acc ess tothe status register is controlled by in somecasesofthe/wppin. 11.1statusregister 11.1.1busy busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, sector erase, block erase , chip erase or write status register instruction. during this time the device will ignor e further instruction except for the read status register and erase suspend instruction (see tw, tpp , tse, tbe1, tbe2 and tce in ac characteristics).when the program, eraseor write status register instructionhas completed, the busybitwillbeclearedtoa0stateindicatingth edeviceisreadyforfurtherinstructions. 11.1.2writeenablelatch(wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing awrite enableinstruction. thewelstatu sbitis cleared to a 0,when device is write disabled. a write disable state occurs upon power up or after any of the following instructions: writedisable,pageprogram,sectorerase,blocker ase,chiperaseandwritestatusregister. 11.1.3blockprotectbits(bp2,bp1,bp0) theblockprotectbits(bp2,bp1,bp0)arenonvola tileread/writebitsinthestatusregister(s4, s3,ands2)thatprovidewriteprotectioncontrola ndstatus.blockprotectbitscanbesetusingthe writestatusregisterinstruction(seetwinaccha racteristics).allnoneoraportionofthememory array can be protected from program and erase instr uctions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 11.1.4top/bottomblockprotect(tb) thenonvolatiletop/bottombit(tb)controlsifth eblockprotectbits(bp2,bp1,bp0)protectfrom the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protectiontable. thefactorydefaultsettingis tb =0. the tbbitcanbesetwiththewritestatus registerinstructiondependingonthestateofthe srp0,srp1andwelbits. 11.1.5sector/blockprotect(sec) thenonvolatilesectorprotectbit(sec)controls iftheblockprotectbits(bp2,bp1,bp0)protect 4kbsectors(sec=1)or64kbblocks(sec=0)intheto p(tb=0)orthebottom(tb=1)ofthearray asshowninthestatusregistermemoryprotectiont able.thedefaultsettingissec=0.
rev.06(aug.18.2010) 14 FM25Q16 11.1.6statusregisterprotect(srp1,srp0) the status register protect bits (srp1 and srp0) ar e nonvolatile read/write bits in the status register (s8 and s7). the srp bits control the meth od of write protection: software protection, hardwareprotection,powersupplylockdownorone timeprogrammable(otp)protection. srp1 srp0 /wp status register description 0 0 x software protection /wppinnocontrol.theregistercanbewrittento afterawriteenableinstruction,wel=1.[factoryd efault] 0 1 0 hardware protected when/wppinislowthestatusregisterlockedand cannot bewrittento. 0 1 1 hardware unprotected when /wp pin is high the status register is unlocke d and canbewrittentoafterawriteenableinstruction, wel=1 1 0 x powersupply lockdown statusregisterisprotectedandcannotbewritten toagain untilthenextpowerdown,powerupcycle (1) . 1 1 x onetime program status register is permanently protected and can no t be writtento. note: 1.whensrp1,srp0=(1,0),apowerdown,powerupcy clewillchangesrp1,srp0to(0,0)state. 11.1.7erasesuspendstatus(sus) thesuspendstatusbitisareadonlybitinthest atusregister(s15)thatissetto1afterexecutin g anerase/programsuspend(75h)instruction.thesus statusbitisclearedto0byerase/program resume(7ah)instructionaswellasapowerdown,p owerupcycle. 11.1.8quadenable(qe) the quad enable (qe) bit is a nonvolatile read/wri te bit in the status register (s9) that allows quad operation.when the qe bit is set to a 0 state (factory default) the /wp pin and /hold are enabled.whentheqepinissettoa1thequadio2 andio3pinsareenabled. warning:theqebitshouldneverbesettoa1dur ingstandardspiordualspioperation ifthe/wpor/holdpinsaretieddirectlytothep owersupplyorground.
rev.06(aug.18.2010) 15 FM25Q16 s6 s0 s7 s1 s2 s3 s4 s5 sec busy srp0 wel bp0 bp1 bp2 tb statusregisterprotect (nonvolatile) sectorprotect (nonvolatile) top/bottomwriteprotect (nonvolatile) writeenablelatch eraseorwriteinprogress blockprotectbits (nonvolatile) figure3a.statusregister1 figure3b.statusregister2
rev.06(aug.18.2010) 16 FM25Q16 11.1.9statusregistermemoryprotection statusregister (1) FM25Q16(16mbit)memoryprotection sec tb bp2 bp1 bp0 block(s) addresses density protion x x 0 0 0 none none none none 0 0 0 0 1 31 1f0000h1fffffh 64kb upper1/32 0 0 0 1 0 30and31 1e0000h1fffffh 128kb upper1/1 6 0 0 0 1 1 28thru31 1c0000h1fffffh 256kb upper1/ 8 0 0 1 0 0 24thru31 180000h1fffffh 512kb upper1/ 4 0 0 1 0 1 16thru31 100000h1fffffh 1mb upper1/2 0 1 0 0 1 0 000000h00ffffh 64kb lower1/32 0 1 0 1 0 0and1 000000h01ffffh 128kb lower1/16 0 1 0 1 1 0thru3 000000h03ffffh 256kb lower1/8 0 1 1 0 0 0thru7 000000h07ffffh 512kb lower1/4 0 1 1 0 1 0thru15 000000h0fffffh 1mb lower1/2 x x 1 1 x 0thru31 000000h1fffffh 2mb all 1 0 0 0 1 31 1ff000h1fffffh 4kb topblock 1 0 0 1 0 31 1fe000h1fffffh 8kb topblock 1 0 0 1 1 31 1fc000h1fffffh 16kb topblock 1 0 1 0 x 31 1f8000h1fffffh 32kb topblock 1 1 0 0 1 0 000000h000fffh 4kb bottomblock 1 1 0 1 0 0 000000h001fffh 8kb bottomblock 1 1 0 1 1 0 000000h003fffh 16kb bottomblock 1 1 1 0 x 0 000000h007fffh 32kb bottomblock
rev.06(aug.18.2010) 17 FM25Q16 11.2instructions the instruction set of the FM25Q16 consists of fift een basic instructions that are fully controlled through the spi bus (see instruction set table). in structions are initiated with the falling edge of chip select (/cs). the first byte of data clocked i nto the di input provides the instruction code. dataonthediinputissampledontherisingedge ofclockwithmostsignificantbit(msb)first. instructions vary in length from a single byte to s everal bytes and may be followed by address bytes,databytes,dummybytes(dontcare),andin somecases,acombination.instructionsare completedwiththerisingedgeofedge/cs.clockr elativetimingdiagramsforeachinstructionare included in figures 4 through 29. all read instruct ions can be completed after any clocked bit. however,allinstructionsthatwrite,programorer asemustcompleteonabyte(/csdrivenhigh afterafull8bithavebeenclocked)otherwisethe instructionwillbeterminated.thisfeaturefurth er protectsthedevicefrominadvertentwrites.additi onally,whilethememoryisbeingprogrammedor erased,orwhenthestatusregisterisbeingwritte n,allinstructionsexceptforreadregisterwill beignoreduntiltheprogramorerasecyclehascom pleted. 11.2.1manufactureranddeviceidentification manufactrerid (m7m0) fidelixsemiconductorserialflash f8h deviceid (id7id0) (id15id0) instruction abh,90h 9fh FM25Q16 14h 3215h
rev.06(aug.18.2010) 18 FM25Q16 11.2.2instructionsettable1 (1) instruction name byte1 (code) byte2 byte3 byte4 byte5 byte6 writeenable 06h writedisable 04h readstatusregister1 05h (s7s0) (2) readstatusregister2 35h (s15s8) (2) writestatusregister 01h (s7s0) (s15s8) pageprogram 02h a23a16 a15a8 a7a0 (d7d0) quaddatainput pageprogram (3) 32h a23a16 a15a8 a7a0 (d7d0,) 3 quadpageprogram 38h a23a0, (d7d0) a15a8 a7a0 (d7d0,) 3 blockerase(64kb) d8h a23a16 a15a8 a7a0 blockerase(32kb) 52h a23a16 a15a8 a7a0 sectorerase(4kb) 20h a23a16 a15a8 a7a0 chiperase c7h/60h erasesuspend 75h eraseresume 7ah powerdown b9h modebitreset (4) ffh release power down/ deviceid abh dummy dummy dummy (id7id0) (5) readmanufacturer/ deviceid (6) 90h dummy dummy 00hor01h (m7m0) (id7id0) readdualmanufacturer/ deviceid (6) efh dummy dummy 00hor01h (m7m0) (id7id0) readquadmanufacturer/ deviceid (6) dfh dummy dummy 00hor01h (m7m0) (id7id0) writesecurityregister 2fh readsecurityregister 2bh (s7s0) entersecuredotp b1h exitsecuredotp c1h readjedecid 9fh (m7m0) manufacturer (id7id0) memorytype (id7id0) capacity notes: 1. databytesareshiftedwithmostsignificantbit first.bytefieldswithdatainparenthesis () indicatedatabeingreadfromthedeviceont heiopin. 2. thestatusregistercontentswillrepeatcontinu ouslyuntil/csterminatestheinstruction.
rev.06(aug.18.2010) 19 FM25Q16 3. quaddatainputpageprograminputdata io0=(d4,d0) io1=(d5,d1) io2=(d6,d2) io3=(d7,d3) 4. this instruction is recommended when using the d ual or quad mode bit feature. see section10.2.28formoreinformation. 5. thedeviceidwillrepeatcontinuouslyuntil/cs terminatestheinstruction. 6. seemanufactureranddeviceidentificationtable fordeviceidinformation. 11.2.3instructionsettable2(readinstructions) instruction name byte1 (code) byte2 byte3 byte4 byte5 byte6 readdata 03h a23a16 a15a8 a7a0 (d7d0) fastreaddata 0bh a23a16 a15a8 a7a0 dummy (d7d0) fastreadduali/o bbh a23a8 (2) a7a0,m7m0 (2) (d7d0,) (1) fastreadquadi/o ebh a23a0,m7m0 (4) (x,x,x,x,d7d0,) (5) (d7d0,) (3) notes: 1:dualoutputdata io0=(d6,d4,d2,d0) io1=(d7,d5,d3,d1) 2:dualinputaddress io0=a22,a20,a18,a16,a14,a12,a10,a8,a6,a4 ,a2,a0,m6,m4,m2,m0 io1=a23,a21,a19,a17,a15,a13,a11,a9,a7,a5 ,a3,a1,m7,m5,m3,m1 3:quadoutputdata io0=(d4,d0) io1=(d5,d1) io2=(d6,d2) io3=(d7,d3) 4:quadinputaddress io0=a20,a16,a12,a8,a4,a0,m4,m0 io1=a21,a17,a13,a9,a5,a1,m5,m1 io2=a22,a18,a14,a10,a6,a2,m6,m2 io3=a23,a19,a15,a11,a7,a3,m7,m3 5:fastreadquadi/odata io0=(x,x,x,x,d4,d0) io1=(x,x,x,x,d5,d1) io2=(x,x,x,x,d6,d2) io3=(x,x,x,x,d7,d3)
rev.06(aug.18.2010) 20 FM25Q16 11.2.4writeenable(06h) the write enable instruction (figure 4) sets the wr ite enable latch (wel) bit in the status registertoa1.thewelbitmustbesetpriortoe verypageprogram,sectorerase,blockerase, chiperaseandwritestatusregisterinstruction.t hewriteenableinstructionisenteredbydriving /cslow,shiftingtheinstructioncode06hintod atainput(di)pinontherisingedgeofclk,and thendriving/cshigh. 0 6 5 4 3 2 1 7 /cs di clk mode 0 mode 3 mode 0 mode 3 instruction (06 h) highimpedance do 0 6 5 4 3 2 1 7 /cs di clk mode 0 mode 3 mode 0 mode 3 instruction (06 h) highimpedance do figure4.writeenableinstructionsequencediagram 11.2.5writedisable(04h) the write disable instruction (figure 5) resets the write enable latch (wel) bit in the status registertoa0.thewritedisableinstructionine nteredbydriving/cslow,shiftingtheinstruction code04hintothedipinandthendriving/cshig h.notethatthewelbitisautomaticallyreset after powerup and upon completion of thewrite sta tus register, page program, sector erase, blockeraseandchiperaseinstructions. 0 6 5 4 3 2 1 7 /cs di clk mode 0 mode 3 mode 0 mode 3 instruction (04 h) highimpedance do 0 6 5 4 3 2 1 7 /cs di clk mode 0 mode 3 mode 0 mode 3 instruction (04 h) highimpedance do figure5.writedisableinstructionsequencediagra m
rev.06(aug.18.2010) 21 FM25Q16 11.2.6readstatusregister1(05h)andreadstatus register2(35h) thereadstatusregisterinstructionsallowthe8b itstatusregistertoberead,theinstructionis enteredbydriving/cslowandshiftingtheinstruc tioncode05hforstatusregister1and35h for status register2 into the di pin on the rising edge of clk. the status register bits are then shiftedoutonthedopinatthefallingedgeofcl kwithmostsignificantbit(msb)firstasshownin figure6.thestatusregisterbitsareshowninfig ure3aand3bincludethebusy,wel,bp2bp0, tb, sec, srp0, srp1 and qe bits (see description of the status register earlier in this datasheet). the status register instruction may be used at any time, even while a program, erase, write securityregisterorwritestatusregistercycleis inprogress.thisallowsthebusystatusbitto be checked to determine when the cycle is complete and if the device can accept another instruction.thestatusregistercanbereadcontin uously,asshowninfigure6.theinstructionis completedbydriving/cshigh. 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(05hor35h) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 statusregisterout /cs clk di do 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 statusregisterout =msb 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(05hor35h) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 statusregisterout /cs clk di do 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 statusregisterout =msb figure6.readstatusregisterinstructionsequence diagram
rev.06(aug.18.2010) 22 FM25Q16 11.2.7writestatusregister(01h) the write status register instruction allows the st atus register to be written. a write enable instructionmustpreviouslyhavebeenexecutedfor thedevicetoacceptthewritestatusregister instruction(statusregisterbitwelmustequal1). oncewriteisenabled,theinstructionisentered bydriving/cslow,sendingtheinstructioncode0 1h,andthenwritingthestatusregisterdatabyte or word as illustrated in figure 7. the status regi ster bits are shown in figure 3 and described earlierinthisdatasheet. onlynonvolatilestatusregisterbitssrp0,sec,t b,bp2,bp1,bp0(bits7,5,4,3,2ofstatus register1) and qe, srp1 (bits 9 and 8 of status re gister2) can be written to. all other status registerbitlocationsarereadonlyandwillnotb eaffectedbythewritestatusregisterinstruction . the/cspinmustbedrivenhighaftertheeighthor sixteenthbitofdatathatisclockedin.ifthis is notdonethewritestatusregisterinstructionwill notbeexecuted.if/csisdrivenhighafterthe eighth clock, the qe and srp1 bits will be cleared to 0. after /cs is driven high, the selftimed writestatusregistercyclewillcommenceforatim edurationoftw(seeaccharacteristics).while the write status register cycle is in progress, the read status register instruction may still be accessedtocheckthestatusofthebusybit.theb usybitisa1duringthewritestatusregister cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the writestatusregistercyclehasfinished,thewrite enablelatch(wel)bitinstatusregisterwill beclearedto0. thewritestatusregisterinstructionallowsthebl ockprotectbits(sec,tb,bp2,bp1andbp0) tobesetforprotectingall,aportion,ornoneof thememoryfromeraseandprograminstructions. protectedareasbecomereadonly(seestatusregist ermemoryprotectiontableanddescription). thewritestatusregisterinstructionalsoallowst hestatusregisterprotectbits(srp0,srp1)to be set. those bits are used in conjunction with the write protect (/wp) pin, lock out or otp features to disable writes to the status register. please refer to 11.1.16 for detailed descriptions statusregisterprotectionmethods.factorydefault allstatusregisterbitsare0. 0 6 5 4 3 2 1 7 /cs di clk mode0 mode3 instruction(01h) highimpedance do 10 9 8 11 12 13 14 15 16 17 18 19 20 21 22 23 mode0 mode3 statusregister1in 7 6 5 4 3 2 x x x x x x 9 8 =msb x x statusregister2in figure7.writestatusregisterinstructionsequenc ediagram
rev.06(aug.18.2010) 23 FM25Q16 11.2.8readdata(03h) thereaddatainstructionallowsonemoredatabyte stobesequentiallyreadfromthememory. the instruction isinitiated by driving the /cs pin low and then shifting the instruction code 03h followedbya24bitaddress(a23a0)intothedip in.thecodeandaddressbitsarelatchedonthe risingedgeoftheclkpin.aftertheaddressisre ceived,thedatabyteoftheaddressedmemory locationwillbeshiftedoutonthedopinatthef allingedgeofclkwithmostsignificantbit(msb) first. the address is automatically incremented to the next higher address after byte of data is shifted out allowing for a continuous stream of dat a. this means that the entire memory can be accessedwithasingleinstructionaslongasthec lockcontinues.theinstructioniscompletedby driving /cs high. the read data instruction sequenc e is shown in figure 8. if a read data instruction is issued while an erase, program or wr ite status register cycle is in process (busy=1)theinstructionisignoredandwillnotha veanyeffectsonthecurrentcycle.theread datainstructionallowsclockratesfromd.ctoam aximumoff r (seeacelectricalcharacteristics). 0 6 5 4 3 2 1 7 /cs di clk mode0 mode3 instruction(03h) highimpedance do 10 9 8 28 29 30 31 32 33 34 35 36 37 38 39 24bitaddress 23 3 2 1 0 =msb 22 21 dataout1 dataout2 7 6 5 4 3 2 1 0 7 figure8.readdataregisterinstructionsequenced iagram
rev.06(aug.18.2010) 24 FM25Q16 11.2.9fastread(0bh) thefastreadinstructionissimilartothereadda tainstructionexceptthatitcanoperateatthe highest possible frequency of f r (see ac electrical characteristics). this is accomp lished by adding eight dummy clocks after the 24bit addres s as shown in figure 9. the dummy clocks allow the devices internal circuits additional tim e for setting up the initial address. during the dummyclocks,thedatavalueonthedopinisado ntcare. 0 6 5 4 3 2 1 7 /cs di clk mode0 instruction(0bh) do 10 9 8 28 29 30 31 24bitaddress 23 3 2 1 0 =msb 22 21 mode3 32 dummybyte 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 dataout1 7 6 5 4 3 2 1 0 dataout2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 /cs di clk do figure9.fastreadregisterinstructionsequenced iagram
rev.06(aug.18.2010) 25 FM25Q16 11.2.10fastreadduali/o(bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read output (0bh) instr uction but with the capability to input the address bits (a230) two bi ts and output data two bits per clock. this reduced instruction overhead may allow for code exe cution (xip) directly from the dual spi in someapplications. the fast read dual i/o instruction can further redu ce instruction overhead through setting the modebits(m70)aftertheinputaddressbits(a23 0),asshowninfigure10a.theuppernibbleof the mode (m74) controls the length of the next fas t read dual i/o instruction through the instructionorexclusionofthefirstbyteinstruct ioncode.thelowernibblebitsofthemode(m30) aredontcare(x),however,theiopinsshouldb ehighimpedancepriortothefallingedgeofthe firstdataoutclock. ifthemodebits(m70)equalaxhex,thenthene xtfastduali/oinstruction(after/csisraised andthenlowered)doesnotrequirethebbhinstruct ioncode,asshowninfigure10b.thisreduces the instruction sequenceby eight clocks and allows theaddress to beimmediately entered after /csisassertedlow.ifmodebits(m70)areanyva lueotheraxhex,thenextinstruction(after/cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a mode bit reset instruction can be used to reset mode bits (m70) before issuing normalinstructions(see11.2.25fordetaileddescr iptions). figure10a.fastreaddualinput/outputinstruction sequencediagram(m70=0xhornotaxh)
rev.06(aug.18.2010) 26 FM25Q16 figure10b.fastreaddualinput/outputinstruction sequencediagram(m70=axh)
rev.06(aug.18.2010) 27 FM25Q16 11.2.11fastreadquadi/o(ebh) the fast read quad i/o (ebh) instruction is similar to thefast read dual i/o (bbh) instruction exceptthataddressanddatabitsareinputandout putthroughfourpinsio 0 ,io 1 ,io 2, andio 3 and four dummy clock are required prior to the data out put. the quad i/o dramatically reduces instruction overhead allowing faster random access for code executing (xip) directly from the quad spi. the quad enable bit (qe) of status regist er2 must be set to enable the fast read quadi/oinstruction. the fast read quad i/o instruction can further redu ce instruction overhead through setting the modebits(m70)aftertheinputaddressbits(a23 0),asshowninfigure11a.theuppernibbleof the mode (m74) controls the length of the next fas t read quad i/o instruction through the instructionorexclusionofthefirstbyteinstruct ioncode.thelowernibblebitsofthemode(m30) aredontcare(x).however,theiopinsshouldb ehighimpedancepriortothefallingedgeofthe firstdataoutclock. ifthemodebits(m70)equalaxhex,thenthene xtfastreadquadi/oinstruction(after/csis raisedandthenlowered)doesnotrequiretheebhi nstructioncode,asshowninfigure11b.this reduces the instruction sequence by eight clocks al lows the address to be immediately entered after /cs is asserted low. if the mode bits (m70) are any value other than ax hex, the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus retuningnormaloperation.amodebitresetcanbe usedtoresetmodebits(m70)beforeissuing normalinstructions(see11.2.25fordetaileddescr iptions.) /cs 0 1 2 3 4 5 6 7 clk mode3 mode0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 instruction(ebh) 4 0 4 0 4 4 0 4 0 4 0 4 0 5 1 5 1 5 5 1 5 1 5 1 5 1 7 3 7 3 7 7 3 7 3 7 3 7 3 io 0 io 1 io 2 io 3 a2316 a158 a70 m70 dummy dummy byte3 byte4 ioswitchesfrom inputtooutput 6 2 6 2 6 6 2 6 2 6 2 6 2 /cs 0 1 2 3 4 5 6 7 clk mode3 mode0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 instruction(ebh) 4 0 4 0 4 4 0 4 0 4 0 4 0 5 1 5 1 5 5 1 5 1 5 1 5 1 7 3 7 3 7 7 3 7 3 7 3 7 3 io 0 io 1 io 2 io 3 a2316 a158 a70 m70 dummy dummy byte3 byte4 ioswitchesfrom inputtooutput 6 2 6 2 6 6 2 6 2 6 2 6 2 byte1 byte2 figure11a.fastreadquadinput/outputinstruction sequencediagram(m70=0xhornotaxh)
rev.06(aug.18.2010) 28 FM25Q16 /cs 0 1 2 3 4 5 6 7 clk mode 3 mode 0 8 9 10 11 12 13 14 15 4 0 4 0 4 5 1 5 1 5 5 1 5 1 5 1 5 1 6 2 6 2 6 6 2 6 2 6 2 6 2 7 3 7 3 7 7 3 7 3 7 3 7 3 io 0 io 1 io 2 io 3 ioswitchesfrom inputtooutput a23 16 a15 8 a70 m70 dummy dummy byte 1 byte 2 4 0 4 0 4 0 4 0 /cs 0 1 2 3 4 5 6 7 clk mode 3 mode 0 8 9 10 11 12 13 14 15 4 0 4 0 4 5 1 5 1 5 5 1 5 1 5 1 5 1 6 2 6 2 6 6 2 6 2 6 2 6 2 7 3 7 3 7 7 3 7 3 7 3 7 3 io 0 io 1 io 2 io 3 ioswitchesfrom inputtooutput a23 16 a15 8 a70 m70 dummy dummy byte 1 byte 2 4 0 4 0 4 0 4 0 figure11b.fastreadquadinput/outputinstruction sequencediagram(m70=axh)
rev.06(aug.18.2010) 29 FM25Q16 11.2.12pageprogram(02h) the page program instruction allows from one byte t o 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locati ons. a write enable instruction must be executedbeforethedevicewillacceptthepagepro graminstruction(statusregisterbitwel=1). the instruction isinitiated by driving the /cs pin low and then shifting the instruction code 02h followed by a 24bits address (a23a0) and at least one data byte, into the di pin. the /cs pin mustbeheldlowfortheentirelengthoftheinstr uctionwhiledataisbeingsenttothedevice.the pageprograminstructionsequenceisshownisfigur e12. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last addre ss byte is not zero, and the number of clocks exceedstheremainingpagelength,theaddressingw illwraptothebeginningofthepage.insome cases,lessthan256bytes(apartialpage)canbe programmedwithouthavinganyeffectonother byteswithinthesamepage.oneconditiontoperfor mapartialpageprogramisthatthenumberof clockscannotexceedtheremainingpagelength.if morethan256bytesaresenttothedevicethe addressingwillwraptothebeginningofthepagea ndoverwritepreviouslysentdata. aswiththewriteanderaseinstructions,the/csp inmustbedrivenhighaftertheeighthbitofthe lastbytehasbeenlatched.ifthisisnotdonethe pageprograminstructionwillnotbeexecuted. after/csisdrivenhigh,theselftimedpageprogr aminstructionwillcommenceforatimeduration of tpp (see ac characteristics).while the page pro gram cycle is in progress, the read status registerinstructionmaystillbeaccessedforchec kingthestatusofthebusybit.thebusybitis a1duringthepageprogramcycleandbecomesa0w henthecycleisfinishedandthedeviceis ready to accept other instructions again. after the page program cycle has finished and write enablelatch(wel)bitinthestatusregisteriscl earedto0.thepageprograminstructionwillnot be executed if the addressed page is protected by t he block protect (sec, tb, bp2, bp1, and bp0)bits, 0 1 2 3 4 5 6 7 instruction (02h) /cs clk mode 3 mode 0 di 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 33 32 35 34 37 36 39 38 7 6 5 4 3 2 1 0 databyte 1 * * /cs clk mode 3 mode 0 di 50 54 53 52 51 55 7 6 5 4 3 2 1 0 databyte 256 40 44 43 42 41 46 45 47 49 48 2072 2 0 73 2074 2 0 75 2076 2 0 77 20 7 8 2079 databyte 3 databyte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 =msb * 0 1 2 3 4 5 6 7 instruction (02h) /cs clk mode 3 mode 0 di 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 33 32 35 34 37 36 39 38 7 6 0 1 2 3 4 5 6 7 instruction (02h) /cs clk mode 3 mode 0 di 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 33 32 35 34 37 36 39 38 7 6 5 4 3 2 1 0 databyte 1 * * /cs clk mode 3 mode 0 di 50 54 53 52 51 55 7 6 5 4 3 2 1 0 databyte 256 40 5 4 3 2 1 0 databyte 1 * * /cs clk mode 3 mode 0 di 50 54 53 52 51 55 7 6 5 4 3 2 1 0 databyte 256 40 44 43 42 41 46 45 47 49 48 2072 2 0 73 2074 2 0 75 2076 2 0 77 20 7 8 2079 databyte 3 databyte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 =msb * figure12.pageprograminstructionsequencediagra m
rev.06(aug.18.2010) 30 FM25Q16 11.2.13quaddatainputpageprogram(32h) thequaddatainputpageprograminstructionallows upto256bytesofdatatobeprogrammed atpreviouslyerased(ffh)memorylocationsusingf ourpins:io 0 , io 1 , io 2 andio 3. thequaddata inputpageprogramcanimproveperformanceforprom programmerandapplicationsthathave slowclockspeed<5mhz.systemwithfasterclocksp eedwillnotrealizemuchbenefitforthequad datainputprograminstructionsincetheinherentp ageprogramtimeismuchgreaterthanthetime ittakestoclockinthedata. tousequaddatainputpageprogramthequadenable instatusregister2mustbeset(qe=1), a write enable instruction must be executed before the device will accept the quad data input pageprograminstruction(statusregister1,wel=1) .theinstructionisinitiatedbydrivingthe/cs pinlowandthenshiftingtheinstructioncode32h followedbya24bitaddress(a23a0)andat leastonedata,intotheiopins.the/cspinmust beheldlowfortheentirelengthoftheinstructio n while data is being sent to the device. all other f unctions of quad data input page program are identical standard page program. the quad data inpu t page program instruction sequence is showninfigure13. 0 1 2 3 4 5 6 7 instruction(32h) / cs clk mode3 mode0 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 33 32 35 34 37 36 39 38 * 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 50 54 53 52 51 55 0 4 0 4 0 40 44 43 42 41 46 45 47 49 48 536 537 538 539 540 541 5 4 2 5 4 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 =msb * byte1 byte2 byte3 byte4 0 1 2 3 4 5 6 7 instruction(32h) / cs clk mode3 mode0 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 0 1 2 3 4 5 6 7 instruction(32h) / cs clk mode3 mode0 8 9 10 24 bitaddress 31 30 29 28 23 3 2 1 0 22 21 33 32 35 34 37 36 39 38 * 33 32 35 34 37 36 39 38 * 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 50 54 53 52 51 2 io 0 io 2 io 3 /cs clk mode3 mode0 50 54 53 52 51 55 0 4 0 4 0 40 44 43 42 41 46 45 47 49 48 536 537 538 539 540 541 5 4 2 5 4 3 byte5 55 0 4 0 4 0 40 44 43 42 41 46 45 47 49 48 536 537 538 539 540 541 5 4 2 5 4 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 =msb * byte1 byte2 byte3 byte4 figure13.quaddatainputpageprograminstruction sequencediagram
rev.06(aug.18.2010) 31 FM25Q16 11.2.14quaddatapageprogram(38h) the quad page program instruction allows 24bit add ress and up to 256 bytes of data to be programmed at previously erased (ffh) memory locati ons using four pins: io 0 , io 1 , io 2 and io 3. thequadpageprogramcanimproveperformanceforp romprogrammerandapplicationsthat haveslowclockspeed<5mhz.systemwithfasterclo ckspeedwillnotrealizemuchbenefitforthe quad page program instruction since the inherent pa ge program time is much greater than the timeittakestoclockinthedata. to use quad page program the quad enable in status register2 must be set (qe=1), awrite enable instruction must be executed before the devi ce will accept the quad page program instruction(statusregister1,wel=1).theinstruc tionisinitiatedbydrivingthe/cspinlowthen shiftingtheinstructioncode38hfollowedbya2 4bitaddress(a23a0)andatleastonedata,into theiopins.the/cspinmustbeheldlowforthee ntirelengthoftheinstructionwhiledataisbeing senttothedevice.allotherfunctionsofquadpag eprogramareidenticalstandardpageprogram. thequadpageprograminstructionsequenceisshown infigure14. 0 1 2 3 4 5 6 7 instruction(38h) / cs clk mode3 mode0 8 9 10 6addresscycle 13 12 11 20 8 4 0 16 12 15 14 17 16 19 18 21 20 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 32 36 35 34 33 37 0 4 0 4 0 22 26 25 24 23 28 27 29 31 30 5 3 6 5 3 7 5 3 8 5 3 9 5 4 0 54 1 5 4 2 54 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 byte 1 byte2 byte3 byte4 21 9 5 1 17 13 22 10 6 2 18 14 23 11 7 3 19 15 0 1 2 3 4 5 6 7 instruction(38h) / cs clk mode3 mode0 8 9 10 6addresscycle 13 12 11 20 8 4 0 16 12 15 14 17 16 19 18 21 20 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 32 36 35 34 33 37 0 4 0 4 0 22 26 25 24 23 28 27 29 31 30 5 3 6 5 3 7 5 3 8 5 3 9 5 4 0 54 1 5 4 2 54 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 byte 1 byte2 byte3 byte4 9 5 1 17 13 10 6 2 18 14 23 11 7 3 19 15 0 1 2 3 4 5 6 7 instruction(38h) / cs clk mode3 mode0 8 9 10 6addresscycle 13 12 11 20 8 4 0 16 12 15 14 17 16 19 18 21 20 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 32 36 35 34 33 37 0 4 0 4 0 22 26 25 24 23 28 27 29 31 30 5 3 6 5 3 7 5 3 8 5 3 9 5 4 0 54 1 5 4 2 54 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 byte 1 byte2 byte3 byte4 21 9 5 1 17 13 22 10 6 2 18 14 23 11 7 3 19 15 0 1 2 3 4 5 6 7 instruction(38h) / cs clk mode3 mode0 8 9 10 6addresscycle 13 12 11 20 8 4 0 16 12 15 14 17 16 19 18 21 20 5 1 5 1 5 1 5 1 4 0 4 0 4 0 4 0 7 3 7 3 7 3 7 3 6 2 6 2 6 2 6 2 io 0 io 2 io 3 /cs clk mode3 mode0 32 36 35 34 33 37 0 4 0 4 0 22 26 25 24 23 28 27 29 31 30 5 3 6 5 3 7 5 3 8 5 3 9 5 4 0 54 1 5 4 2 54 3 byte5 4 0 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte6 byte7 byte10 byte11 byte8 byte9 byte12 io 1 io 0 io 2 io 3 io 1 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 5 1 6 2 7 3 byte253 byte254 byte255 byte256 byte 1 byte2 byte3 byte4 9 5 1 17 13 10 6 2 18 14 23 11 7 3 19 15 figure14.quadpageprograminstructionsequenced iagram
rev.06(aug.18.2010) 32 FM25Q16 11.2.15sectorerase(20h) the sector erase instruction sets all memory within a specified sector (4kbytes) to the erased stateofall1s(ffh).awriteenableinstructionm ustbeexecutedbeforethedevicewillacceptthe sector erase instruction (status register bit wel m ust equal 1). the instruction is initiated by driving the /cs pin low and shifting the instructio n code 20h followed a 24bit sector address (a23a0).thesectoreraseinstructionsequenceis showninfigure15. the/cspinmustbedrivenhighaftertheeighthbi tofthelastbytehasbeenlatched.ifthisisnot done the sector erase instruction will not be execu ted. after /cs is driven high, the selftimed sectoreraseinstructionwillcommenceforatimed urationoftse(seeaccharacteristics).while thesectorerasecycleisinprogress,thereadsta tusregisterinstructionmaystillbeaccessed for checking the status of the busy bit. the busy b it is a 1 during the sector erasecycle and becomesa0whenthecycleisfinishedandthedevi ceisreadytoacceptotherinstructionsagain. after the sector erase cycle has finished thewrite enable latch (wel) bit in status register is clearedto0.thesectoreraseinstructionwillnot beexecutediftheaddressedpageisprotected bytheblockprotect(sec,tb,bp2,bp1,andbp0)b its(seestatusregistermemoryprotection table). figure15.sectoreraseinstructionsequencediagra m
rev.06(aug.18.2010) 33 FM25Q16 11.2.1632kbblockerase(52h) theblockeraseinstructionsetsallmemorywithin aspecifiedblock(32kbytes)totheerasedstate ofall1s(ffh).awriteenableinstructionmustbe executedbeforethedevicewillaccepttheblock eraseinstruction(statusregisterbitwelmustequ al1).theinstructionisinitiatedbydrivingthe /cspinlowandshiftingtheinstructioncode52h followeda24bitblockaddress(a23a0).the blockeraseinstructionsequenceisshowninfigure 16. the/cspinmustbedrivenhighaftertheeighthbi tofthelastbytehasbeenlatched.ifthisisnot donetheblockeraseinstructionwillnotbeexecut ed.after/csisdrivenhigh,theselftimedblock erase instruction will commence for a time duration of tbe1 (see ac characteristics).while the block erase cycle is in progress, the read status r egister instruction may still be accessed for checking the status of the busy bit. the busy bit i s a 1 during the block erase cycle and becomesa0whenthecycleisfinishedandthedevi ceisreadytoacceptotherinstructionsagain. after the sector erase cycle has finished thewrite enable latch (wel) bit in status register is clearedto0.theblockeraseinstructionwillnotb eexecutediftheaddressedpageisprotectedby the block protect (sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure16.32kbblockeraseinstructionsequencedi agram
rev.06(aug.18.2010) 34 FM25Q16 11.2.1764kbblockerase(d8h) theblockeraseinstructionsetsallmemorywithin aspecifiedblock(64kbytes)totheerasedstate ofall1s(ffh).awriteenableinstructionmustbe executedbeforethedevicewillaccepttheblock eraseinstruction(statusregisterbitwelmustequ al1).theinstructionisinitiatedbydrivingthe /cspinlowandshiftingtheinstructioncoded8h followeda24bitblockaddress(a23a0).the blockeraseinstructionsequenceisshowninfigure 17. the/cspinmustbedrivenhighaftertheeighthbi tofthelastbytehasbeenlatched.ifthisisnot donetheblockeraseinstructionwillnotbeexecut ed.after/csisdrivenhigh,theselftimedblock erase instruction will commence for a time duration of tbe1 (see ac characteristics).while the block erase cycle is in progress, the read status r egister instruction may still be accessed for checking the status of the busy bit. the busy bit i s a 1 during the block erase cycle and becomesa0whenthecycleisfinishedandthedevi ceisreadytoacceptotherinstructionsagain. aftertheblockerasecyclehasfinishedthewrite enablelatch(wel)bitinthestatusregisteris clearedto0.theblockeraseinstructionwillnot beexecutediftheaddressedpageisprotectedby the block protect (sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). * highimpedance /cs di 23 2 1 0 22 0 1 2 3 4 5 6 7 instruction(d8h) clk mode3 mode0 8 9 24bitaddress 31 30 29 mode3 mode0 do =msb * * highimpedance /cs di 23 2 1 0 22 0 1 2 3 4 5 6 7 instruction(d8h) clk mode3 mode0 8 9 24bitaddress 31 30 29 mode3 mode0 do =msb * figure17.64kbblockeraseinstructionsequencedi agram
rev.06(aug.18.2010) 35 FM25Q16 11.2.18chiperase(c7h/60h) thechiperaseinstructionsetsallmemorywithint hedevicetotheerasedsateofall1s(ffh).a writeenableinstructionmustbeexecutedbeforeth edevicewillacceptthechiperaseinstruction (statusregisterbitwelmustequal1).theinstruc tionisinitiatedbydrivingthe/cspinlowand shiftingtheinstructioncodec7hor60h.thec hiperaseinstructionsequenceisshowninfigure 18. the/cspinmustbedrivenhighaftertheeighthbi thasbeenlatched.ifthisisnotdonethechip erase instruction will not be executed. after /cs i s driven high, the selftimed chip erase instruction will commence for a time duration of tc e (see ac characteristics). while the chip erasecycleisinprogress,thereadstatusregiste rinstructionmaystillbeaccessedtocheckthe statusofthebusybit.thebusybitisa1during thechiperasecycleandbecomesa0when thecycleisfinishedandthedeviceisreadytoac ceptotherinstructionsagain.afterthechiperase cyclehasfinishedthewriteenablelatch(wel)bit inthestatusregisterisclearedto0.thechip eraseinstructionwillnotbeexecutedifanypage isprotectedbytheblockprotect(sec,tb,bp2, bp1,andbp0)bits(seestatusregistermemoryprot ectiontable). figure18.chiperaseinstructionsequencediagram
rev.06(aug.18.2010) 36 FM25Q16 11.2.19erasesuspend(75h) the erase suspend instruction 75h allows the syst em to interrupt a sector or block erase operation and then read from or program data to, an y other sector or block. the write status registerinstruction(01h)anderaseinstructions( 20h,52h,d8,c7h,60h)arenotallowedduring suspend.erasesuspendisvalidonlyduringthesec tororblockeraseoperation.ifwrittenduring thechiperaseorprogramoperation,theerasesusp endinstructionisignored.amaximumoftime oftsus(seeaccharacteristics)isrequiredtos uspendtheeraseoperation.thebusybitinthe statusregisterwillclearto0aftererasesuspend . 0 1 2 3 4 5 6 7 /cs clk mode3 mode0 mode3 mode0 instruction(75h) di highimpedance acceptreadorprogram instruction tsus do figure19.erasesuspendinstructionsequence 11.2.20eraseresume(7ah) theeraseresumeinstructionmustbewrittentores umethesectororblockeraseoperationafter anerasesuspend.afterissuedthebusybitinthe statusregisterwillbesettoa1andthesector or block will complete the erase operation. erase r esume instruction will be ignored unless an erasesuspendoperationisactive. figure20.eraseresumeinstructionsequence
rev.06(aug.18.2010) 37 FM25Q16 11.2.21powerdown(b9h) although the standby current during normal operatio n is relatively low, standby current can be furtherreducedwiththepowerdowninstruction.th elowerpowerconsumptionmakesthepower down instruction especially useful for battery powe red applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by d riving the /cs pin low and shifting theinstruction codeb9hasshowninfigure21. the/cspinmustbedrivenhighaftertheeighthbi thasbeenlatched,ifthisisnotdonethepower down instruction will not be executed. after /cs is driven high, the powerdown state will be enteredwithinthetimedurationoftdp(seeaccha racteristics).whileinthereleasepowerdown /deviceidinstruction,whichrestoresthedevicet onormaloperation,willberecognized.allother instructions are ignored. this includes the read st atus register instruction, which is always availableduringnormaloperation.ignoringallbut oneinstructionmakesthepowerdownstatea useful condition for securing maximum write protect ion. the device always powersup in the normaloperationwiththestandbycurrentoficc1. figure21.deeppwerdowninstructionsequencediag ram
rev.06(aug.18.2010) 38 FM25Q16 11.2.22releasepowerdown/deviceid(abh) thereleasefrompowerdown/deviceidinstruction isamultipurposeinstruction.itcanbeused toreleasethedevicefromthepowerdownstateor obtainthedeviceelectronicidentification(id) number. toreleasethedevicefromthepowerdownstate,th einstructionisissuedbydrivingthe/cspin low,shiftingtheinstructioncodeabhanddrivin g/cshighasshowninfigure22a.releasefrom powerdown will take the time duration of tres1 (se e ac characteristics) before the device will resume normal operation and other instructions are accepted. the /cs pin must remain high duringthetres1timeduration. whenusedonlytoobtainthedeviceidwhilenotin thepowerdownstate,instructionisinitiated bydrivingthe/cspinlowandshiftingtheinstruc tioncodeabhfollowedby3dummybytes.the deviceidbitsarethenshiftedonthefallingedge ofclkwithmostsignificantbit(msb)firstas showninfigure22b. thedeviceidvalueforthefm 25q16islistedinmanufactureranddevice identification table. the device id can be read con tinuously. the instruction is completed by driving/cshigh. when used to release the device from the powerdow n state and obtain the device id, the instructionisthesameaspreviouslydescribed,an dshowninfigure22b,exceptthatafter/csis driven high it must remain high for a time duration of tres2 (see ac characteristics). after this time duration the device will resume normal operati on and other instructions will be accepted. if the release from powerdown /device id instruction isissued while an erase, program orwrite cycleisinprocess(whenbusyequals1)theinstru ctionisignoredandwillnothaveanyeffects onthecurrentcycle. 0 1 2 3 4 5 6 7 /cs clk mode3 mode0 mode3 mode0 instruction(abh) di highimpedance powerdowncurrent standbycurrent tres1 0 1 2 3 4 5 6 7 /cs clk mode3 mode0 mode3 mode0 instruction(abh) di highimpedance powerdowncurrent standbycurrent tres1 do 0 1 2 3 4 5 6 7 /cs clk mode3 mode0 mode3 mode0 instruction(abh) di highimpedance powerdowncurrent standbycurrent tres1 0 1 2 3 4 5 6 7 /cs clk mode3 mode0 mode3 mode0 instruction(abh) di highimpedance powerdowncurrent standbycurrent tres1 do figure22a.releasepowerdowninstructionsequence
rev.06(aug.18.2010) 39 FM25Q16 0 1 2 3 4 5 6 7 instruction(abh) /cs clk mode3 mode0 di 8 9 10 3dummybytes 31 30 29 28 23 3 2 1 0 22 21 * highimpedance 35 34 33 32 37 36 38 3 2 1 0 7 6 5 4 * powerdowncurrent standbycurrent mode3 mode0 deviceid ** tres2 =msb * ** 0 1 2 3 4 5 6 7 instruction(abh) /cs clk mode3 mode0 di 8 9 10 3dummybytes 31 30 29 28 23 3 2 1 0 22 21 * highimpedance 35 34 33 32 37 36 38 3 2 1 0 7 6 5 4 * powerdowncurrent standbycurrent mode3 mode0 deviceid ** tres2 =msb * ** 0 1 2 3 4 5 6 7 instruction(abh) /cs clk mode3 mode0 di 8 9 10 3dummybytes 31 30 29 28 23 3 2 1 0 22 21 * highimpedance 35 34 33 32 37 36 38 0 1 2 3 4 5 6 7 instruction(abh) /cs clk mode3 mode0 di 8 9 10 3dummybytes 31 30 29 28 23 3 2 1 0 22 21 * highimpedance 35 34 33 32 37 36 38 3 2 1 0 7 6 5 4 * powerdowncurrent standbycurrent mode3 mode0 deviceid ** tres2 =msb * ** figure22b.releasepowerdown/deviceidinstruct ionsequencediagram
rev.06(aug.18.2010) 40 FM25Q16 11.2.23readmanufacturer/deviceid(90h),(efh),(d fh) thereadmanufacturer/deviceidinstructionisan alternativetothereleasefrompowerdown/ device id instruction that provides both the jedec assigned manufacturer id and the specific deviceid. the read manufacturer/ device id instruction is ver y similar to the release from powerdown / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instructioncode90horefhordfhfollowedb ya24bitaddress(a23a0)of000000h.after which,themanufactureridforfidelixsemiconducto r(f8h)andthedeviceidareshifted outonthefallingedgeofclkwithmostsignifican tbit(msb)firstasshowninfigure23a,23bor 23c.thedeviceidvaluefortheFM25Q16islisted inmanufactureranddeviceidentificationtable. ifthe24bitaddressisinitiallysetto000001ht hedeviceidwillbereadfirstandthenfollowedb y themanufacturerid.themanufactureranddeviceid scanbereadcontinuously,alternatingfrom onetotheother.theinstructioniscompletedbyd riving/cshigh. figure23a.readmanufacturer/deviceiddiagram
rev.06(aug.18.2010) 41 FM25Q16 figure23b.readdualmanufacturer/deviceiddiagr am
rev.06(aug.18.2010) 42 FM25Q16 figure23c.readquadmanufacturer/deviceiddiagr am
rev.06(aug.18.2010) 43 FM25Q16 11.2.24jedecid(9fh) for compatibility reasons, the FM25Q16 provides sev eral instructions to electronically determine theidentityofthedevice.thereadjedecidinstr uctioniscompatiblewiththejedecstandard forspicompatibleserialmemoriesthatwasadopted in2003.theinstructionisinitiatedbydriving the /cs pin low and shifting the instruction code 9fh. the instruction jedec assigned manufacturer id byte for fidelix semiconductor(f8h) and two device id bytes, memory type(id15id8)andcapacity(id7id0)arethenshi ftedoutonthefallingedgeofclkwithmost significant bit (msb) first shown in figure 24. for memory type and capacity values refer to manufacturer and device identification table. the j edec id can be read continuously. the instructioniscompletedbydriving/cshigh. 0 1 2 3 4 5 6 7 instruction (9fh) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 memorytypeid 15id8 capacityid7id0 di do =msb * 0 1 2 3 4 5 6 7 instruction ) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance 0 1 2 3 4 5 6 7 instruction ) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 memorytypeid 15id8 capacityid7id0 di do =msb * 0 1 2 3 4 5 6 7 instruction (9fh) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance 0 1 2 3 4 5 6 7 instruction (9fh) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 memorytypeid 15id8 capacityid7id0 di do =msb * 0 1 2 3 4 5 6 7 instruction ) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance 0 1 2 3 4 5 6 7 instruction ) /cs clk mode3 mode0 di 8 9 10 11 12 13 14 15 manufacturerid (4ah) do highimpedance /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 /cs clk mode3 mode0 21 20 19 18 17 16 27 26 25 24 23 22 31 30 29 28 32 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 memorytypeid 15id8 capacityid7id0 di do =msb * figure24.readjedecid
rev.06(aug.18.2010) 44 FM25Q16 11.2.25modebitreset(ffh) for fast read dual/quad i/o operations, mode bits ( m70) are implemented to further reduce instructionoverhead.bysettingthemodebits(m7 0)toaxhex,thenextfastreaddual/quad i/ooperationsdonotrequirethebbh/ebhinstructi oncode(see11.2.10fastreadduali/oand 11.2.11 fastreadquadi/ofordetaildescriptions ). ifthesystemcontrollerisresetduringoperation itwilllikelysendastandardspiinstruction,suc h asreadid(9fh)orfastread(0bh),totheFM25Q16 .however,aswithmostspiserialflash memories,theFM25Q16doesnothaveahardwarerese tpin,soifmodebitsaresettoaxhex, the FM25Q16 will not recognize any standard spi ins truction. to address this possibility, it is recommended to issue a mode bit reset instruction ffh as the first instruction after a system reset.doingsowillreleasethemodebitsforthe axhexstateandallowstandardspiinstruction toberecognized.themodebitsresetinstructioni sshowninfigure25. don tcare 0 1 2 3 4 5 6 7 instruction(ffh) don tcare don tcare /cs clk mode3 mode0 mode3 mode0 io 0 io 1 io 2 io 3 don tcare 0 1 2 3 4 5 6 7 instruction(ffh) don tcare don tcare /cs clk mode3 mode0 mode3 mode0 io 0 io 1 io 2 io 3 figure25.modebitsresetforfastreaddual/quad i/o
rev.06(aug.18.2010) 45 FM25Q16 11.2.26entersecuredotp(b1h) the enter secured otp instruction is for entering t he additional 4kbitsecured otp mode. the additional4kbitsecuredotpisindependentfromm ainarray,whichmaybeusedtostoreunique serialnumberforsystemidentifier.afterentering thesecuredotpmode,andthenfollowstandard readorprogram,proceduretoreadoutthedataor updatedata.thesecuredotpdatacannotbe updatedagainonceitislockdown please note that wrsr/wrscur commands are not accep table during the access of secure otpregion,oncesecurityotpislockdown,onlyco mmandsrelatedwithreadarevalid. theentersecuredotpinstructionsequenceisshown infigure26. 0 1 2 3 4 5 6 7 instruction(b1h) /cs clk mode3 mode0 mode3 mode0 di 0 1 2 3 4 5 6 7 instruction(b1h) /cs clk mode3 mode0 mode3 mode0 di figure26.entersecuredotpinstructionsequence 11.2.27exitsecuredotp(c1h) theexitsecuredotpinstructionisforexitingthe additional4kbitsecuredotpmode. theexitsecuredotpinstructionsequenceisshown infigure27 0 1 2 3 4 5 6 7 instruction(c1h) /cs clk mode3 mode0 mode3 mode0 di 0 1 2 3 4 5 6 7 instruction(c1h) /cs clk mode3 mode0 mode3 mode0 di figure27.exitsecuredotpinstructionsequence
rev.06(aug.18.2010) 46 FM25Q16 11.2.28readsecurityregister(2bh) thereadsecurityregisterinstructionisforreadi ngthevalueofsecurityregisterbits.theread securityregistercanbereadatanytime(evenin program/erase/writestatusregistercondition) andcontinuously. thedefinitionofthesecurityregisterbitsisas below: secured otp indicator bit. the secured otp indicator bit shows the chip is loc ked by factory beforeexfactoryornot.whenitis0,itindica tesnonfactorylock,1indicatesfactorylock. lockdownsecuredotp(ldso)bit. bywritingwrscurinstruction,theldsobitmaybe set to1forcustomerlockdownpurpose.however,onc ethebititsetto1(lockdown),theldso bit and the 4kbit secured otp area cannotbe updat ed any more.while itisin 4kbitsecured otpmode,arrayaccessisnotallowedtowrite. 7 6 5 4 3 2 1 0 7 securityregisterout =msb 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(2bh) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 securityregisterout /cs clk di do 7 6 5 4 3 2 1 0 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(2bh) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 securityregisterout /cs clk di do 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 securityregisterout =msb 7 6 5 4 3 2 1 0 7 securityregisterout =msb 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(2bh) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 securityregisterout /cs clk di do 7 6 5 4 3 2 1 0 0 6 5 4 3 2 1 7 mode 0 mode 3 instruction(2bh) 11 10 9 8 12 13 17 16 18 19 15 14 21 20 23 22 securityregisterout /cs clk di do 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 securityregisterout =msb figure28.readsecurityregisterinstructionseque nce securityregisterdefinition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x ldso (indicateif lockdown) secured otp indicatorbit reserved reserved reserved reserved reserved reserved 0=notlock down 1=lock down(cannot program/erase otp) 0=non factorylock 1=factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non volatilebit non volatilebit
rev.06(aug.18.2010) 47 FM25Q16 11.2.29writesecurityregister(2fh) thewritesecurityregisterinstructionisforchan gingthevaluesofsecurityregisterbits.unlike write status register, the wren instruction is not required before writing wrscur instruction. thewrscurinstructionmaychangethevalueofbit1 (ldsobit)forcustomertolockdownthe 4kbit secured otp area. once the ldso bit is set t o 1, the secured otp area cannot be updatedanymore. the/csmustgohighexactlyattheboundary;other wise,theinstructionwillberejectedandnot executed. 0 6 5 4 3 2 1 7 / cs di clk mode 0 mode 3 instruction (2 fh ) highimpedance do mode 0 mode 3 0 6 5 4 3 2 1 7 / cs di clk mode 0 mode 3 instruction (2 fh ) highimpedance do mode 0 mode 3 0 6 5 4 3 2 1 7 / cs di clk mode 0 mode 3 instruction (2 fh ) highimpedance do mode 0 mode 3 0 6 5 4 3 2 1 7 / cs di clk mode 0 mode 3 instruction (2 fh ) highimpedance do mode 0 mode 3 figure29.writesecurityregisterinstructionsequ ence
rev.06(aug.18.2010) 48 FM25Q16 11.34kbitsecuredotp its for unique identifier to provide 4kbit oneti meprogram area for setting device unique serial numberwhichmaybesetbyfactoryorsystemcustom er.pleaserefertotableof4kbitsecured otpdefinition. securityregisterbit0indicateswhetherthech ipislockedbyfactoryornot. to program the 4kbit secured otp by entering 4k bit secured otp mode (with enso command)andgoingthroughnormalprogramprocedure ,andthenexiting4kbitsecuredotp modebywritingexsocommand customer may lockdown bit1 as 1. please refer to table of security register definition for security register bit definition and table of 4kb it secured otp definition for address range definition. note.oncelockdownwhateverbyfactoryorcust omer,itcannotbechangedanymore.while in4kbitsecuredotpmode,arrayaccessisnotall owedtowrite. 4kbitsecuredotpdefinition addressrange size standard factorylock customerlock 000000~00000f 128bit esn (electricalserialnumber) 000010~0001ff 3968bit n/a determinedbycustomer
rev.06(aug.18.2010) 49 FM25Q16 12.electricalcharacteristics 12.1absolutemaximumratings (1) parameters symbol conditions range unit supplyvoltage vcc 0.6to+4.0 v voltageappliedtoanypin v io relativetoground 0.6tovcc+4.0 v transientvoltageonanypin v iot <20nstransient relativetoground 2.0vtovcc+2.0v v storagetemperature t stg 65 to+150 ?c leadtemperature t lead seenote (2) ?c electrostaticdischarge voltage v esd human bodymodel (3) 2000to+2000 v notes: 1.thisdevicehasbeendesignedandtestedforthe specifiedoperationranges.properoperation outside of these levels is not guaranteed. exposure to absolute maximum rating may affect devicereliability.exposurebeyondabsolutemaximu mratingsmaycausepermanentdamage. 2.compliantwithjedecstandardjstd20cforsmal lbodysnpborpbfree(green)assembly andtheeuropeandirectiveonrestrictionsonhazar doussubstances(rohs)2002/95/eu. 3.jedecstdjesd22a114a(c1=100pf,r1=1500ohms,r 2=500ohms). 12.2operatingranges spec parameter symbol conditions min max unit supplyvoltage vcc f r =85 ? ,f r =50 ? , 2.7 3.6 v temperature,operating tj industrial 40 +85 ?c
rev.06(aug.18.2010) 50 FM25Q16 12.3enduranceanddataretention parameter conditions min max unit erase/programcycles 4kbsector,32/64kbblockorf ullchip. 100,000 cycles dataretention fulltemperaturerange 20 years 12.4poweruptimingandwriteinhibitthreshold spec parameter symbol min max unit vcc(min)to/cslow tvsl (1) 10 ? timedelaybeforewriteinstruction tpuw (1) 1 10 ? writeinhibitthresholdvoltage vwi (1) 1 2 v note: 1.theseparametersarecharacterizedonly. vcc(max) vcc(min) vwi vcc program.eraseandwriteinstructionsareignored /csmusttrackvcc tvsl readinstructions allowed deviceisfully accessible tpuw reset state time vcc(max) vcc(min) vwi vcc program.eraseandwriteinstructionsareignored /csmusttrackvcc tvsl readinstructions allowed deviceisfully accessible tpuw reset state time figure30.poweruptimingandvoltagelevels
rev.06(aug.18.2010) 51 FM25Q16 12.5dcelectricalcharacteristics spec parameter symbol condition min typ max unit inputcapacitance cin (1) vin=0v (2) 6 ? outputcapacitance cout (1) vout=0v (2) 8 ? inputleakage ili 2 ? i/oleakage ilo 2 ? standbycurrent icc1 /cs=vcc, vin=gndorvcc 10 50 ? powerdowncurrent icc2 /cs=vcc, vin=gndorvcc 1 5 ? currentreaddata/ dual/quad1 ? (2) icc3 c=0.1vcc/0.9vcc io=open 4/5/6 6/7.5/9 ? currentreaddata/ dual/quad33 ? (2) icc3 c=0.1vcc/0.9vcc io=open 6/7/8 9/10.5/12 ? currentreaddata/ dual/quad50 ? (2) icc3 c=0.1vcc/0.9vcc io=open 7/8/9 10/12/13.5 ? currentreaddata/ dual/quad85 ? (2) icc3 c=0.1vcc/0.9vcc io=open 10/11/12 15/16.5/18 ? currentwrite statusregister icc4 /cs=vcc 8 12 ? currentpage program icc5 /cs=vcc 20 25 ? current sector/block erase icc6 /cs=vcc 20 25 ? currentchiperase icc7 /cs=vcc 20 25 ? inputlowvoltages vil 0.5 vccx0.2 v inputhighvoltages vih vccx0.8 vcc+0.4 v outputlowvoltages vol iol=1.6 ? 0.4 v output highvoltages voh ioh=100 ? vcc0.2 v notes: 1. tested on sample basis and specified through des ign and characterization data, ta = 25?c, vcc=3v. 2.checkedboardpattern.
rev.06(aug.18.2010) 52 FM25Q16 12.6acmeasurementconditions spec parameter symbol min max unit loadcapacitance c l 30 ? inputriseandfalltimes t r, t f 5 ? inputpulsevoltages v in 0.2vcctoo.8vcc v inputtimingreferencevoltages in 0.3vcctoo.7 vcc v outputtimingreferencevoltages out 0.5vcctoo. 5vcc v note: 1. outputhizisdefinedasthepointwheredatao utisnolongerdriven. 0.5vcc 0.8vcc 0.2vcc inputlevels inputandoutput timingreferencelevels 0.5vcc 0.8vcc 0.2vcc inputlevels inputandoutput timingreferencelevels 0.5vcc 0.8vcc 0.2vcc inputlevels inputandoutput timingreferencelevels figure31.acmeasurementi/owaveform
rev.06(aug.18.2010) 53 FM25Q16 12.7acelectricalcharacteristics spec description symbol alt min typ max unit clockfrequency forallinstructions,exceptreaddata(03h) 2.7v3.6vvcc&industrialtemperature f r f c d.c. 85 ? clockfrequency forallinstructions,exceptreaddata(03h) 3.0v3.6vvcc&commercialtemperature f r f c d.c. 104 ? clockhigh,lowtimeexceptreaddata(03h) tclh, tcll (1) 4 ? clockhigh,lowtimeforreaddata(03h) instructions tcrlh, tcrll (1) 6 ? clockrisetimepeaktopeak tclch (2) 0.1 v/ ? clockfalltimepeaktopeak tchcl (2) 0.1 v/ ? /csactivesetuptimerelativetoclk tslch tcss 7 ? /csnotactiveholdtimerelativetoclk tchsl 5 ? datainsetuptime tdvch tdsu 4 ? datainholdtime tchdx tdh 4 ? /csactiveholdtimerelativetoclk tchsh 7 ? /csnotactivesetuptimerelativetoclk tshch 7 ? /cs deselect time (for read instructions/ write, eraseandprograminstructions) tshsl tcsh 10/40 ? outputdisabletime tshqz (2) tdis 7 ? clocklowtooutputvalid 2.7v3.6v/3.0v3.6v tclqv tv 7/6 ? outputholdtime tclqx tho 0 ? /holdactivesetuptimerelativetoclk thlch 7 ?
rev.06(aug.18.2010) 54 FM25Q16 12.8acelectricalcharacteristics(contd) spec description symbol alt min typ max unit /holdactiveholdtimerelativetoclk tchhh 5 ? /holdnotactivesetuptimerelativetoclk thhch 7 ? /holdnotactiveholdtimerelativetoclk tchhl 5 ? /holdtooutputlowz thhqx (2) t lz 7 ? /holdtooutputhighz thlqz (2) t hz 12 ? writeprotectsetuptimebefore/cslow twhsl (3) 20 ? writeprotectsetuptimeafter/cshigh tshwl (3) 100 ? /cshightopowerdownmode tdp (2) 3 ? /cshightostandbymodewithoutelectronic signatureread tres1 (2) 3 ? /cshightostandbymodewithelectronic signatureread tres2 (2) 1.8 ? /cshightonextinstructionaftersuspend tsus (2) 20 ? writestatusregistertime tw 10 15 ? byteprogramtime t bp 10 150 ? pageprogramtime t pp 1.5 5 ? sectorerasetime(4kb) t se 40 300 ? blockerasetime(32kb) t be1 200 1000 ? blockerasetime(64kb) t be2 300 1500 ? chiperasetimeFM25Q16 t ce 10 50 s notes: 1.clockhigh+clocklowmustbelessthanorequa lto1/fc. 2.valueguaranteedbydesignand/orcharacterizati on,not100%testedinproduction. 3.onlyapplicableasaconstraintforawritestat usregisterinstructionwhensectorprotectbitis setto1. 4.commercialtemperatureonlyappliestofastread (f r1 &f r2 ).industrialtemperatureappliesto allotherparameters.
rev.06(aug.18.2010) 55 FM25Q16 12.9serialoutputtiming 12.10inputtiming 12.11holdtiming
rev.06(aug.18.2010) 56 FM25Q16 13.packagespecification 13.18pinsoic150mil millimeters inches symbol min max min max a 1.47 1.72 0.058 0.068 a1 0.10 0.24 0.004 0.009 a2 1.45 0.057 b 0.33 0.50 0.013 0.020 c 0.19 0.25 0.0075 0.098 d (3) 4.8 4.95 0.189 0.195 e 5.8 6.19 0.228 0.244 e1 (3) 3.8 4.00 0.150 0.157 e (2) 1.27bsc 0.050bsc l 0.40 1.27 0.015 0.050 0 ? 8 ? 0 ? 8 ? y 0.076 0.003 notes: 1.controllingdimensions:inches,unlessotherwise specified. 2.bsc=basicleadspacingbetweencenters. 3.dimensionsdande1donotincludemoldflashpr otrusionsandshouldbemeasuredfromthe bottomofthepackage.
rev.06(aug.18.2010) 57 FM25Q16 13.28pinsoic208mil millimeters inches symbol min max min max a 1.75 2.16 0.069 0.085 a1 0.05 0.25 0.002 0.010 a2 1.70 1.91 0.067 0.075 b 0.35 0.48 0.014 0.019 c 0.19 0.25 0.007 0.010 d 5.18 5.38 0.204 0.212 e 7.70 8.10 0.303 0.319 e1 5.18 5.38 0.204 0.212 e 1.27bsc 0.050bsc l 0.50 0.80 0.020 0.031 0? 8? 0? 8? y 0.10 0.004 notes: 1.controllingdimensions:inches,unlessotherwise specified. 2.bsc=basicleadspacingbetweencenters. 3.dimensionsdande1donotincludemoldflashpr otrusionsandshouldbemeasuredfromthe bottomofthepackage. 4. formed leads shall be planar with respect to one another within. 0004 inches at the seating plane.
rev.06(aug.18.2010) 58 FM25Q16 13.38pinpdip300mil dimensionininch dimensioninmin symbol min nom max min nom max a 0.210 5.334 a 1 0.015 0.381 a 2 0.125 0.130 0.135 3.18 3.30 3.43 b 0.016 0.018 0.022 0.41 0.46 0.56 b 1 0.058 0.060 0.064 1.47 1.52 1.63 c 0.008 0.010 0.014 0.20 0.25 0.36 d 0.360 0.365 0.370 9.14 9.27 9.40 e 0.290 0.300 0.310 7.37 7.62 7.87 e 1 0.245 0.250 0.255 6.22 6.35 6.48 e 1 0.090 0.100 0.110 2.29 2.54 2.79 l 0.120 0.130 0.140 3.05 3.30 3.56 0 15 0 15 ea 0.335 0.355 0.375 8.51 9.02 9.53 s 0.045 1.14
rev.06(aug.18.2010) 59 FM25Q16 13.48contact6x5wson millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.0276 0.0295 0.0315 a1 0.00 0.02 0.05 0.0000 0.0008 0.0019 a2 0.55 0.0126 a3 0.19 0.20 0.25 0.0075 0.0080 0.0098 b 0.36 0.40 0.48 0.0138 0.0157 0.0190 d (3) 5.90 6.00 6.10 0.2320 0.2360 0.2400 d1 3.30 3.40 3.50 0.1299 0.1338 0.1377 e 4.90 5.00 5.10 0.1930 0.1970 0.2010 e1 (3) 4.20 4.30 4.40 0.1653 0.1692 0.1732 e (2) 1.27bsc 0.0500bsc k 0.20 0.0080 l 0.50 0.60 0.75 0.0197 0.0236 0.0295
rev.06(aug.18.2010) 60 FM25Q16 13.58contact6x5wsoncontd. millimeters inches symbol min typ. max min typ. max solderpattern m 3.40 0.1338 n 4.30 0.1692 p 6.00 0.2360 q 0.50 0.0196 r 0.75 0.0255 notes: 1. advanced packaging information; please contact f idelix semiconductor for the latest minimumandmaximumspecifications. 2.bsc=basicleadspacingbetweencenters. 3.dimensionsdande1donotincludemoldflashpr otrusionsandshouldbemeasuredfromthebottom ofthepackage. 4. themetal pad areaon the bottom center of the p ackage isconnected to the deviceground (gnd pin).avoidplacementofexposedpcbbiasunderthe pad.
rev.06(aug.18.2010) 61 FM25Q16 13.616pinsoic300mil millimeters inches symbol min max min max a 2.36 2.64 0.093 0.104 a1 0.10 0.30 0.005 0.012 b 0.33 0.51 0.013 0.020 c 0.18 0.28 0.007 0.000 d (3) 10.08 10.49 0.397 0.413 e 10.01 10.64 0.394 0.419 e1 (3) 7.39 7.59 0.291 0.299 e (2) 1.27bsc 0.050 l 0.39 1.27 0.015 0.050 0? 8? 0? 8? y 0.076 0.003 notes: 1.controllingdimensions:inches,unlessotherwise specified. 2.bsc=basicleadspacingbetweencenters. 3.dimensionsdande1donotincludemoldflashpr otrusionsandshouldbemeasuredfromthe bottomofthepackage.
rev.06(aug.18.2010) 62 FM25Q16 14.orderinginformation


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